• darkcalling@lemmygrad.ml
    ·
    edit-2
    1 year ago

    It doesn't have NSA backdoors in the design so it's unacceptable for domestic use and they don't want it to take off for foreign use because then they can't spy on other countries. (Same rationale behind banning Huawei, never was about Chinese backdoors, was about lack of NATO backdoors that was the issue and always will be with any Chinese products).

    Even assuming a lack of built in backdoors, the west controlling the companies responsible for these things mean they can sit in the pipe of their security disclosures and pick out zero days disclosed to the company, exploit them against enemies first before those enemies even know it. If they're Chinese companies they can't do that.

    There's zero evidence China behaves like the western bandits and hoodlums and plenty pointing to the fact China keeps business (selling you good working products) and spying (gathering intelligence) separate. They won't sell you a trojan horse, they'll just hack you, having no particular advantage because of secret knowledge or back-doors. Which is the way things should be in the type of world the west claims to be for in their alleged desire for free markets and free trade.

      • nephs@lemmygrad.ml
        ·
        edit-2
        1 year ago

        Exactly. An add instruction, or any instruction needs to be carried out in steps within the hardware. Sometimes there's systematic bugs in these implementations that can be exploited.

        Plus, it's an open architecture where those bugs can be exposed and fixed. Where in Intel/arm based architectures, they can be rolled out to the world and be used by those in the know.

        Eg: https://www.techrepublic.com/article/is-the-intel-management-engine-a-backdoor/

        • ShiningWing@lemmygrad.ml
          ·
          1 year ago

          RISC-V being open doesn't mean all implementations using it have to be, though

          There's nothing stopping a manufacturer from putting their own Intel Management Engine equivalent in a RISC-V CPU