I stole 20 minutes of labour from work to make this
VPMADD52HUQ - Multiplies packed unsigned 52-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 52-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 104-bit intermediate results. The low 52-bit, unsigned integer of each 104-bit product is added to the corresponding qword unsigned integer of the destination operand (the first operand) under the writemask k1.
What the fuck is wrong with these people
Mind you apparently it's not completely out of the blue: seems to be particularly useful for modular exponentiation in encryption
yeah but where's the instruction if I want to multiply packed unsigned 53-bit integers in each qword element of the first source operand (the second operand) with the packed unsigned 53-bit integers in the corresponding elements of the second source operand (the third operand) to form packed 106-bit intermediate results?
I've always said that encryption would be so much better if only we used 53 bit integers instead of 52 😢
Every single instruction has a concrete usecase. Otherwise they wouldn't exist. but yeah, that one is so extremely specific, it prompted me to make that
why the fuck is it 52-bit integers? that's a data type in literally no language, even if there's some use case where the missing 12 bits are used by the software for metadata or other stuff.
Significand, mantissa, the part after the decimal point. (Or maybe the term “significand” includes the implicit “1.” and so would be 53 bits? I forget.)
Anyway, the part that isn’t exponent or sign, not including the implicit 1, is 52 bits.
Years and years ago I had a hard copy of the Intel CPU manuals (they used to ship them at no charge upon request). The instruction set alone consumed two volumes, each of which was over an inch thick.
We are talking about CPU instructions :)
CISC means "Complex instruction set computing" (basically what AMD/Intel are doing) which stands in opposition to RISC "Reduced instruction set computing" like ARM :)
I don't understand, I code using a magnetic nanotube-tipped needle and a steady hand.
You mind if I repost this with credit on the fediverse?
:mao-wave:
I’m stealing labour from work right now reading this and laying on my couch as I had too much coffee.
:solidarity:
I had to deal with support for itanium once, and i think there is no single other architecture I hate this much
